The present invention relates to integrated circuit (IC) chip reliability and, more specifically, to a method for improving integrated circuit chip reliability through reliability-optimized selective voltage binning.
More particularly, various failure mechanisms can cause the components (e.g., devices, interconnects, etc.) of an integrated circuit (IC) chip to degrade. These failure mechanisms include, but are not limited to, time-dependent dielectric breakdown (TDDB) of the gate dielectric layer or between metal lines, hot carrier injection (HCI), negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), soft error rate (SER), retention disturbance, stress migration (SM) (also referred to as stress-induced voiding (SIV)) and electromigration (EM). Over time these failure mechanisms can impact performance (e.g., operating speed) and/or lead to IC chip failure. Therefore, it would be advantageous to provide a method that minimizes the impact of such failure mechanisms in order to improve IC chip reliability.